The present invention relates to buffers for driving a capacitive load at high speed, and particularly to buffers which are capable of being integrated in CMOS technology. A typical application of the disclosed innovations is the driving of the output nodes of an integrated circuit which must operate at a high switching speed, such as a memory or like device.
When an output buffer of an integrated circuit switches the voltage on its output node between logic levels in order to transfer a certain datum from an input node thereof to the external world, an inductive overvoltage is generated on the supply rails (V.sub.DD and V.sub.SS).
The induced overvoltage is given by ##EQU1## , where L.sub.para is parasitic line inductance (typically from a few nH up to about 15 nH), and I.sub.out is the output current which is delivered by the buffer (in order to quickly charge or discharge the capacitance of a load connected to its output node). This overvoltage (commonly referred to as switching noise) may reach such a level as to be prejudicial to correct functioning of the integrated circuit which includes the buffer. The problem is aggravated by the fact that, in many cases, a single integrated circuit may include a plurality of output nodes having similar drive requirements in terms of speed and of capacitive load (e.g. the data outputs of a high-speed memory), where the occurrence of a simultaneous switching on a large number of output nodes is possible.
The problem of reducing the switching noise without excessively penalizing the switching speed has already been tackled in a number of proposals. For example, EP-A-0,284,357 filed on Mar. 22, 1988 by S. Oshima et al., entitled "Semiconductor Integrated Circuit Having a Data Output Buffer Circuit", suggests to maintain "separate" the supply pads and metal lines of the "internal" portion of the integrated circuit from dedicated supply pads and metal lines for powering the buffers, in order to reduce the noise which is induced on the supply lines of the internal circuitry of the device upon the switchings of the output voltage. This is motivated by the fact that the greater contribution to the parasitic inductance of a supply line is due to the connecting wire (bonding wire) between pad and pin. This approach is certainly useful, but insufficient.
Another known technique for reducing the switching noise consists in introducing appropriate phase shifts between the switching of different output nodes, in order to avoid summing the effects of a simultaneous parallel switching sign of different nodes.
Another similar technique consists in replacing a single pull-up and a single pull-down transistor of the buffer with respective sets of paralleled transistors, while also suitably phase-shifting the switchings of the multiple pull-up and/or pull-down transistors of a buffer..sup.1 These techniques have the drawback of depending strongly from the fabrication process, and in any case they need an accurate experimental characterization. FNT .sup.1 See Wong et al., "An 11-ns 8K.times.18 CMOS Static RAM with 0.5 .mu.m Devices", 23 IEEE J.SOLID-STATE CIRCUITS 1095-1103 (Oct. 1988), which is hereby incorporated by reference.
Several techniques are known which are based on precharging the output node to an intermediate voltage level, between V.sub.SS and V.sub.DD before effecting the switching..sup.2 In this way, the voltage swing on the output node at the switching instant is somewhat reduced, and so also is the time-variation of the current associated with the switching. This technique is useful when there is a dead time between a "request" for a new datum and the actual reading thereof, as for example in memory circuits, as will be evident to one of ordinary skill in the art. FNT .sup.2 See T. Wada et at., "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", 22 IEEE J.SOLID-STATE CIRCUITS 727-732 (Oct. 1987), or H. Okuyama et al., "A 7-ns 32K.times.8 CMOS SRAM", 23 IEEE J.SOLID-STATE CIRCUITS 1054-1059 (Oct. 1988), both of which are hereby incorporated by reference.
A similar technique is described in EP-A-0,271,331, filed on Dec. 9, 1987 by S. Takayasu, entitled: "Semiconductor Integrated Circuit". According to this reference, a precharge of the output node is carried out only when the starting output level is a logic high ("1") and is performed for reaching an output voltage value capable of appearing as a logic high level if it is applied to the input of an electronic circuit (e.g. 2.5 V). Conversely, when the starting output level is a logic low ("0"), a precharge is not performed because such a situation is not considered critical.
These precharge techniques, when applied to memories, alleviate the problem but do not eliminate it.
Another technique having a wide application for reducing the switching noise consists in controlling the driving of the pull-up and pull-down output transistors in such a way that the output current I.sub.out that is delivered has a peak value of its time derivative (dI.sub.out /dt) as low as possible, subject to compatibility with switching speed requirements. For example, it has been proposed to drive the gates of the pull-up and pull-down output transistors through a series resistance, or from logic circuits which are supplied through series resistances to the positive and/or to the negative supply rails. This serves to slow down, through a pre-established time constant, the rise and fall of the driving voltage which is applied to said gate electrodes, thus making the variation of the output current which is delivered by the buffer less abrupt..sup.3 Performing such control of the driving voltages by means of active networks has also been proposed..sup.4 FNT .sup.3 See EPC Application EP-A-0,251,910, filed on Jun. 25, 1987, by M. Naganuma, entitled: "CMOS Output Buffer Circuit," or Wang et al., "A 21-ns 32K.times. 8 CMOS Static RAM with a Selectively Pumped p-Well Array", 22 IEEE J. SOLID STATE CIRCUITS 704-711 (Oct. 1987), both of which are hereby incorporated by reference. FNT .sup.4 See Gubbels et al., "A 40-ns/100pF Low-Power Full-CMOS 256K (32K.times.8) SRAM", 22 IEEE J. SOLID-STATE CIRCUITS 741-747 (Oct. 1987); or Chu et al., "A 25-ns Low-Power Full-CMOS 1-Mbit (128.K.times.8) SRAM", 23 IEEE J. SOLID-STATE CIRCUITS 1078-1084 (Oct. 1988), both of which are hereby incorporated by reference.
In a co-pending commonly owned application with overlapping inventorship (Franco Maloberti, Salvatore Portaluri, and Guido Torelli, "Fast Capacitive-Load Driving Circuit for Integrated Circuits, Particularly Memories"),.sup.5 which is hereby incorporated by reference, an output buffer is described wherein the output pull-up and pull-down transistors are driven by use of purposely generated voltage ramps, in order to reduce the switching noise. FNT .sup.5 The U.S. application is 07/811,323, filed Dec. 20, 1991; the priority application (Italian App'n 22569 A/90) was filed on Dec. 28, 1991.
In general, the state of the art is such that there is room for further improving the performance of such output buffers in terms of minimizing the overvoltages induced on the supply lines (switching noise), while simultaneously ensuring a high speed which, in the case of memories, would permit attainment of extremely small access times.